The present application relates to semiconductor device fabrication, and more particularly, to a method for reducing parasitic capacitance between the gate electrode and source/drain contacts.
One of the major challenges for field effect transistor (FET) scaling is the increased parasitic capacitance that transistor components exhibit when reduced to smaller scales. As one example, as the feature sizes of transistors continue to shrink, the parasitic capacitance between the source/drain contacts and the gate electrode increases. The result is a degradation in the overall performance of the scaled down device. Therefore, there remains a need to provide FETs having lower parasitic capacitance between the gate electrode and source/drain contacts.